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Thread: Bulldozer 20 Questions: Part 1 ~

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    Default Bulldozer 20 Questions

    Bulldozer 20 Questions: Part 1

    You’ve sent in your questions and we’ve begun to sort through them to pull out the best. There were plenty of common themes that were arising, so we’ll be grouping some of the bigger categories together. I am going to tackle some of the easiest ones first because some of the more technical questions will need to go to the engineers. We’ll handle this blog in four rounds, with 5 questions each.
    Let’s get started.

    ” There has been some confusion among those in the tech community regarding the actual CPU architecture, with ‘modules’ and ‘cores’ being explained differently by different people. “
    – Waffle911


    Yes, there has definitely been some confusion about modules and cores. Modules are only our way of laying out the subcomponents of the processor. You will not see us market modules as they are largely invisible to everyone but the designers. Operating systems, for instance, will enumerate the integer cores, seeing a 16-core AMD Operton™ processor (currently codenamed “Interlagos”) as 16 cores, not 8 modules. Modules do impact the way that certain CPU features are addressed – a discussion of which we’ll save for a later date – but in general we will focus on cores and not modules. The reason that we have modules is to help cut down on a lot of redundant circuitry in the processor. With multiple cores there is lots of duplication and this eats up die space and increases power draw. There are areas within the processor that can be shared because there is no major impact on performance, and other areas that should not be shared because they create bottlenecks.
    You will never see a spec sheet with modules called out. Modules will not have a “marketing name”, they will only be “”Bulldozer” modules.” In reality, modules will only matter to the designers. Since we went out with ”Bulldozer” information very early we focused on the shared architecture and talked at the module level (it is still far too early to be sharing die shots….) Because of this the two most misunderstood theories became a.) the module was the whole processor and b.) the module was somehow equal to one core.
    When we talk about cores we will always be using the most agreed upon definition of cores – the integer logic. Today most workloads are integer with a much smaller portion being floating point. This is why we focused on integer cores as the most logical way to define a core.
    Each integer core will be able to run one software thread, and these threads can all be done simultaneously, unlike an SMT-type technology that lets two threads share one core. You typically find SMT technology on processors with much lower core counts, and its shared nature can create bottlenecks, even resulting in negative throughput in some cases.
    As for core counts, here is what we have committed to at this point:

    • “Interlagos” – 16-core server processor
    • “Valencia” – 8-core server processor
    • “Zambezi” – 8-core client processor

    “What are the virtualization advantages of “Bulldozer” relative to current AMD and “Bulldozer” time-frame Intel architectures?” – Muzaffer Kal

    Well, to begin with, the competition has not revealed anything about their virtualization features in that timeframe so I will stick with AMD comparisons.
    One of the most striking and easy comparisons to make is the pure core count. In my experience, customers today tend to use the “one VM per core” rule of thumb. In today’s world that means up to 24 VMs for a 2P AMD Opteron™ 6100 Series platform (12 cores per processor x 2 processors = 24 cores = 24 VMs), and up to 32 VMs for a 16-core, “Bulldozer”-based 2P “Interlagos” system. Or you can run several robust multi-core VMs on a server; for example, you could run up to eight VMs on an “Interlagos” system, each with 4 vCPUs.
    Although we will not be releasing technical details yet, some of the new features include making the caches more efficient, preserving live migration compatibility between our cores, and more effectively managing changes to virtual machines such that hypervisor interactions are limited.
    In addition to a greater number of cores, the upcoming “Bulldozer” platform will feature L2 cache that will be shared between integer cores. So for those customers pinning VMs to cores, they have the ability to build a 2P VM, and tie it to two cores that share a common L2 cache. This can help cut down on some of the cache latency as the VM’s two cores have all of the adjacent shared cache lines in a single location.
    There will also be some significant enhancements to our memory controller. This is the first major memory controller overhaul since the introduction of the Quad-Core AMD Opteron processor back in 2007. Back then, everyone was looking at virtualization, but not as many were deploying it. These new memory controller enhancements were designed with virtualization in mind so that there are more optimizations around the memory handling for virtualization.
    Someone else had also asked about support for Hyper V and older OS’s. We plan to support Hyper V in the future, just as we do today. In terms of older OS’s – there will be some limitations mainly because older OS’s were developed at a time when processors had fewer cores and supported less memory. An older OS can always be run as guest OS on a virtualized server. AMD collaborates with Microsoft to ensure that new processors are well supported by a range of OS versions. We will publish more info as we approach launch.

    “The x86 core (Bobcat) of AMD Fusion APU Ontario will be based on Bulldozer architecture?”
    – Fabio Mendes

    Actually, these are different designs. The upcoming “Ontario” processor will be based on the “Bobcat” core, which has a different core architecture than “Bulldozer.” There have been some that have made the assumption that a Bobcat was just a scaled down “Bulldozer”, but they are, in fact, different. I’m sure that between the two there are similarities and some small sub-components that are shared, but you won’t see the modular design of “Bulldozer” in “Bobcat.”

    Will Bulldozer get a Turbo CORE for single threaded applications, just like the Thuban?”
    – Björn

    Yes. There will be a Turbo CORE feature for “Bulldozer”, but there will be some improvements from what you see in “Thuban” (our 6-core AMD Phenom™ processor). There are some enhancements to give it more “turbo”. This will be the first introduction of the Turbo CORE technology in the server processors. We expect that this will translate into a big boost in performance when using single threaded applications, and there should be some interesting capabilities for heavier workloads as well. We’re pretty excited about how this will be implemented with “Bulldozer”, but the specifics of how this is implemented and the expected performance gains will not be disclosed until launch.

    “Which architectural decision for Bulldozer has the biggest impact for server-class products and how does it achieve that impact?”
    – Andrew Cowley

    That is actually a tougher question than it sounds because it depends on what you are looking to impact. I personally believe that what most customers are looking for is better performance per watt with each generation of product. Or, to be more specific, people are looking for greater performance and scalability, but they want to do it in the same power/thermal envelopes that they are used to with today’s servers.
    The modular architecture really allows us to do this with “Bulldozer”. In today’s processors there is a lot of circuitry that sits idle for most cycles; it needs to be there for the peak, but most of the time it is just sitting. That not only eats up power, but adds to the die space (think: cost.)
    By creating a modular architecture you have the ability to reduce/share a lot of the circuits that are lightly used, which can help cut down on power consumption and cost.
    For those that want more performance, cutting down on the power consumption means that you can get higher clock speeds within the same power/thermal envelopes.
    For those looking for lower overall power consumption, the modular architecture helps in that aspect as well.
    Because of this modular architecture, we can increase the core count, so if you are interested in database, HPC or virtualization, that higher core count – with real cores – will help boost performance for your applications.
    But the key to an architecture like this is understanding how to push the limits, but not go too far. Sharing everything results in low power consumption, but terrible performance. Sharing nothing results in higher performance, but you get hammered by the power consumption and the cost of the die. So the key to a modular architecture will be how successfully you plan the shared components to maximize your design goals.
    Stay tuned, in the next update we will cover floating point, compilers and power efficiency.
    http://blogs.amd.com/work/2010/08/23...ons-round-one/
    Last edited by Lil' ½ Dead; 30-08-2010 at 22:23.

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    Bulldozer 20 Questions: Part 2

    Here is the second set of answers from our 20 Questions blog. I am leaving the last 2 blogs (final 10 answers) until after the Hot Chips event. We’ll be unveiling new information there and I am pretty sure that will drive a lot of questions.

    “Will Bulldozer implement new versions of Hypertransport?” – Rheo

    No, Bulldozer takes advantage of the same version of HyperTransport™ (HT) technology as our existing AMD Opteron™ 4000 and 6000 series processors, HyperTransport 3.1.

    “Is there any”programmable-tangible” improvement in synchronization between cores in the same module? In other words, will I get tangible performance improvement if I can partition my multi-threaded algorithm to pairs of closely interacting threads, and schedule each pair to a module?”
    – Edward Yang

    That is a very interesting question.
    For the majority of software, the OS will work in concert with the processor to manage the thread to core relationships. We are collaborating with Microsoft and the open source software community to ensure that future versions of Windows and Linux operating systems will understand how to enumerate and effectively schedule the Bulldozer core pairs. The OS will understand if your machine is setup for maximum performance or for maximum performance/watt which takes advantage of Core Performance Boost.
    However, let’s say you want to explore if you can get a performance advantage if your threads were scheduled on different modules. The benefit you can gain really depends on how much sharing the two threads are going to do.
    Since the two integer cores are completely separate and have their own execution clusters (pipelines) you get no sharing of data in the L1 – and there is no specific optimizations needed at the software level. However, at the L2 cache level there could be some benefits. A shared L2 cache means that both cores have access to read the same cache lines – but obviously only one can write any cache line at any time. This means that if you have a workload with a main focus of querying data and your two threads are sharing a data set that fits in our L2, then having them execute in the same module could have some advantages. The main advantage we expect to see is an increase in the power efficiency of the cores that are idle. The more idle other cores are, the better chance the busy cores will have to boost.
    However, there is another consideration to this which is how available other cores are. You need to weigh the benefits of data sharing with the benefit of starting the thread on the next available core. Stacking up threads to execute in proximity means that a thread might be waiting in line while an open core is available for immediate execution. If your multi-threaded application isn’t optimized to target the L2 (or possibly the L3 cache), or you have distinctly separate applications to run, and you don’t need to conserve power, then you’ll likely get better performance by having them scheduled on separate modules. So it is important to weigh both options to determine the best execution.

    “How much extra performance will we see when running two-threaded applications on one Bulldozer Module compared to two cores in different modules?”
    – Simon

    Without getting too specific around actual scaling across cores on the processor, let me share with you what was in the Hot Chips presentation. Compared to CMP (chip multiprocessing – which is, in simplistic terms building a multicore chip with each core having its own dedicated resources) two integer cores in a Bulldozer module would deliver roughly 80% of the throughput. But, because they have shared resources, they deliver that throughput at low power and low cost. Using CMP has some drawbacks, including more heat and more die space. The heat can limit performance in addition to consuming more power. Ask yourself, would you rather have a 4-cylinder engine that delivered 300HP or a 6-cylinder engine that delivered 360HP and consumed less gas? The cylinder to horsepower ratio for 4-cylinder is obviously higher (75HP/cylinder vs. the V6’s 60HP/cylinder), meaning that each cylinder can give you more performance. However, looking at the overall enginge, you are getting less total output; and you are getting that lower output at a higher cost (higher gas consumption).

    “Current and forthcoming Nehalem EX based servers from IBM and HP top out at 8 sockets and 64 cores. What kind of vertical scalability can we expect from Bulldozer-based servers?”
    – David Roff

    Bulldozer will fit into the current “Maranello” and “San Marino/Adelaide” platforms. “Maranello” is our high performance platform that will support up to 4 CPUs. Combining a “Maranello” platform with the upcoming 16-core “Interlagos” processors, the total core density of a 4P system will reach as many as 64 cores.
    The 8P x86 market today is pretty small. According to IDC, last year it accounted for roughly 7,915 total servers, down 26% from the year before (Source: IDC Quarterly Server Tracker, Q4 2009). If you want to say that 2009 was a bad year, from 2007 to 2008 the 8P x86 market was essentially flat as well, so that isn’t a growth engine. Part of what is impacting that market is the core and memory densities of today’s systems. People bought 8P servers to get to 48 cores (8 x 6-core) or to get to large memory footprints. Today’s 4P systems are meeting those needs at a lower price, with lower power consumption and lower latency. When we get to 2011 with “Bulldozer,” you’ll see an increase up to 64 cores, and we expect the total memory footprint will increase again.
    The bottom line is, you’ll get the 64 cores that you want, you’ll just have to spend a lot less to get them; is that OK?

    “As far as power usage goes, from what I understand BD is supposed to be taking power management features to a level of granularity that hasn’t been seen yet with consumer/business grade CPUs. Will those new features be available to current MC users or will a platform upgrade be necessary? Can you elaborate on any new power saving features that would make a business want to consider BD at this time?”
    – Jeremy Stewart

    Current “Maranello” platforms with AMD Opteron™ 6100 Series processors already have the hooks embedded in them for any “Bulldozer”-level power efficiency features. When we specified the platforms for today’s processors, we did so with “Bulldozer” in mind.
    As we have said already in this blog, we expect the shared architecture to provide us with a great deal of power savings – there are a lot of circuits that are essentially being duplicated in today’s multicore processors. Having a new “from the ground up” design allowed us to take a very close look at the circuits and determine which ones are ripe for consolidation and which ones really need their own dedicated resources.
    We started with inherently power-efficient microarchitecture and implementation that included dynamic sharing of shared resources, minimized data movement and took advantage of extensive clock and power gating. From there, we added active management support that allows us to digitally measure activity in order to estimate power. Support for chip-level core power gating was also added to the processor.
    These new features join existing AMD Opteron processor technologies such as AMD PowerNow!™, AMD CoolCore™, low voltage DDR-3 memory support and more, all working in concert to help create a power efficient system.
    Even though you’ll see processors with 33% more cores and larger caches than the previous generation, we’ll still be fitting them into the same power and thermal ranges that you see with our existing 12-core processors.
    http://blogs.amd.com/work/2010/08/30...%80%93-part-2/

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    Wowawesome info,but AMD did'nt mention the socket compatibilty
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    Quote Originally Posted by Biff73 View Post
    Wowawesome info,but AMD did'nt mention the socket compatibilty
    There will be 2 more parts

    Maybe it'll come up in the future.

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    Quote Originally Posted by Lil' ½ Dead View Post
    There will be 2 more parts

    Maybe it'll come up in the future.
    I can't waitWhen is part 2?
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    Quote Originally Posted by Biff73 View Post
    I can't waitWhen is part 2?
    Part 2 is posted above. I don't know when exactly AMD will post part 3

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    Quote Originally Posted by Lil' ½ Dead View Post
    Part 2 is posted above. I don't know when exactly AMD will post part 3
    Part 3 will defintely make either a lot of AMD users very happy or sad,if it mentions which Socket type bulldozer will sit on
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    Quote Originally Posted by Biff73 View Post
    Part 3 will defintely make either a lot of AMD users very happy or sad,if it mentions which Socket type bulldozer will sit on
    I believe bulldozer is Socket AM3+. So much shizza going on I can't remember. I may be getting older too.
    Last edited by Drdeath; 02-09-2010 at 01:34.

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    Quote Originally Posted by Drdeath View Post
    I believe bulldozer is Socket AM3+. So much shizza going on I can't remember. I may be getting older too.
    Don't believe,just assume that AMD will follow the same plans as AM2+/AM3,don't tell me this does not make you happy
    1. Ryzen 9 3900X/Alphacool monsta 360 with 6x Infineon Loop RGB fans/EK CPU Water block/Aorus X570 Extreme/2x Zotac RTX 2080 SLI/Corsair Vengeance Pro RGB 3200Mhz 4x16gb/2x Samsung 960 Pro 1 TB ssd, 4x Lexar NM100 512Gb ssd/Asus Xonar D2X/2xDell U2713h/Seasonic X 1200W/AsiaHorse pink sleeve cable set/Thermaltake Core P5 TG

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    Bulldozer 20 Questions: Part 3

    “Can we get a dual socket overclockable board with 2-PCI-e X16 slots plus pcie-8,etc..Solid state caps,IE: all the top parts” – David Hunt

    Client systems will be available in single socket version. The two socket client market is very small and getting smaller every quarter. It hit its peak a few years ago with dual core (giving you 4 total cores), but quad core processors essentially crushed that market. Now the fact that you will get 8 cores in a single socket will probably wipe out what little is left in that market. It is hard to justify putting the resources into a market that was, at its peak, .8% of the total client market and exited Q4 of last year at .4% of the client market.
    AMD OpteronTM processors will be available in dual socket systems, but those will not have the overclocking capability that you are looking for. Server customers do not manually overclock their systems; they need to ensure reliability. While you can run a processor outside of its specified operating range (overclocking it to a higher frequency), when you do that you take on some risks.
    First, you diminish the useful life of the processor. By how much is hard to say because all processors are different. But overclocking increases the potential for failure, not something you want on a server. Secondly, when you overclock, sometimes your results are not what you expected. 2+2=5. Not a problem if you are playing a game, but a real problem if you are using a server to run automated systems, make business decisions or keep financial records straight.
    Marketing AMD OpteronTM Processors as “overclockable” would not help us in growing server share in the commercial market (and most likely hurt us), so it is not something that we will be pursuing.

    “How much NUMA architecture will the Bulldozer be, or in other words, if I have a 4-socket Bulldozer how much will memory access differ between access to memory local to the socket and access to memory from other CPUs in the box.“
    – Mikael Ronström

    With Non-Uniform Memory Access (NUMA) each processor has its own memory controller and its own memory banks (local access). Processors can also access memory from the other processors in the system (remote access.) NUMA enables this access.
    In the past, in a 4P system, some memory locations were 2 hops away, leading to greater latency. In today’s current AMD Opteron™ 4000 and 6000 Series platforms, there are enough HyperTransport™ technology links that all of the remote memory calls are only one hop away.
    There will be enhancements to our memory controllers, things we can’t talk about just yet, that we expect to help reduce the time to access memory, both locally and remotely.
    HT Assist, a feature that was introduced with our six-core AMD OpteronTM processors, helps reduce memory traffic and speed up memory access from remote locations.
    As for actual memory access timings, I will leave that for launch.

    “Can you explain how is your Multi-threading technology different from Intels? What are the advantages?”
    - Vygantas

    We use actual, physical cores to handle multiple threads. Intel does this too, but they use HyperThreading technology to execute two threads on a single core as well which can create bottlenecks.
    The challenge with HT is that it exploits gaps in the execution pipeline in order to get that second thread running. In a world where you have inefficiently executing applications, you have gaps in the pipeline and you can get that second thread executing. But, in efficient software, you have less opportunity to take advantage and you potentially end up with little or no gain. Some applications actually recommend turning off HT for better performance.
    We will have cores, real physical cores, and that leads to better overall scalability. In heavily optimized systems, you aren’t fighting over execution pipelines because every thread has its own integer core. There is less system overhead involved in parsing out the threads because cores are all pretty much equal.
    Take this scenario: a 4 core processor with HyperThreading with have all 4 physical cores actively handling threads. Now you need to execute a 5th thread. Do you put that thread on an already active core, reducing the processing of the thread already on that core because the two threads now have to share the same execution pipeline, or, do you wait a cycle and hope that one of those cores frees up? There is a lot more decision making when you have “big cores and HT cores”, but in the AMD world, you could have 8 or 16 cores, so the 5th thread just goes onto the next available physical core. It is much easier and much more scalable.

    “What kind of compiler support will Bulldozer class cores receive from your partners and will intel’s ICC compiler have the support for Bulldozer’s AVX instruction set(and not discriminate it via CPUID flag like in the past with previous Opterons)?”
    – Ivan

    We are working with all of the key compiler vendors to help ensure support of Bulldozer. We are spending a lot of time working with the Open64 compiler folks to make sure that there is support, as well as the PGI Group, GCC compiler and of course, Microsoft®.
    AVX will require applications to be recompiled in order to take advantage of 256-bit floating point (either ours or our competitors).
    I can’t comment on the ICC compiler, I recommend asking them that question.

    “Please explain why having two separate integer cores is better than one fat one. For example, if each core has two ALUs and two AGUs and 16 KB of L1 cache, what if it was one integer core with 4 ALUs and 4 AGUs and 32KB cache? Theoretically, you’d get about the same performance for multi-threaded programs and better single threaded performance.”
    – Ryan

    We get asked that a lot. The key is that a single core that would be able to compete with the throughput of two smaller cores would consume a disproportionate amount of die space and consume more power. Taking Bulldozer and turning each module into one “big core” instead of two cores with some shared resources would net you a disproportionately higher price and disproportionately higher power consumption.
    In reality what we are doing is driving efficiency. And don’t worry about the single threaded performance –we have already stated publicly that Bulldozer single threaded performance is expected to be higher than our current core architectures.
    What you have to keep in mind is that we are bringing innovation and driving towards the future. Back in 2005 when we did the first x86 dual core processors, there were some that argued that single core processors were better because a.) they had higher clock speed and b.) no applications really take advantage of multiple cores. Where are those people today?
    When we innovated with bringing x86-64 to the market there were those that said 32-bit applications were better because they were faster and nobody really needs to access more than 2GB in most cases anyway. Where are those people today?
    In this business you can either look out the windshield and focus on the road ahead and the technology that is coming up in the future or look in the rear view mirror and constantly obsess about how things were in the past.
    The rules are changing now, just as they did in the past. AMD will continue to innovate.
    http://blogs.amd.com/work/2010/09/13...stions-part-3/

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    Bulldozer 20 Questions: Part 4

    Well folks, here are the final set of answers.

    “Hi AMD-people, when scaling from 12 to 16 cores (MC to Interlagos) will you be able to still maintain the thermal design envelope without cutting down on clockspeeds? Sorry for my bad english ” – Kenny


    Well, as we have said before, we are not revealing some things until launch (clock speeds, cache sizes, pricing, benchmarks or the launch date) but I can say that from a clock speed perspective the base clocks speeds will be very competitive in our opinion. Please keep in mind that we will have AMD Turbo CORE technology in these processors, so the actual frequencies can be higher than the base frequencies in many, if not all, workloads. We have made some improvements to Turbo CORE technology that we cannot share just yet, but I can say that the way we have implemented it with “Bulldozer” overcomes some of the limitations in previous turbo implementations.
    TDPs are all planned to be the same between current AMD Opteron™ 6100 and 4100 series processors with the new “Bulldozer”-based processors (codenamed “Interlagos” and “Valencia,” Respectively).

    “How much resemblance does your today’s Bulldozer architecture have to the original design?” – Tye


    As you are aware, when we initially designed “Bulldozer,” we were working with a more modular processor design. The original “Bulldozer” design was 45nm. But as development progressed, it became clear that the 45nm design that we had been working on was not going to be as competitive as we would have liked.
    With the world watching your every move, all product decisions become very public (how many articles have you seen about “Bulldozer” in the press?) It is never an easy decision to make substantial changes to your product roadmap, but sometimes you have to make the tough call because it is the right thing to do. It helps when your partners are behind you and agree with the changes – sometimes a little short-term pain is necessary for a long-term gain.
    We obviously aren’t going to get into specific design changes, but we think that the 32nm “Bulldozer” can bring a lot of benefit to our product due to smaller transistor size (which can help drive down the power envelope). By going for lower power, we hope to give you more room for compute cores, FP capabilities and more.
    In addition, bringing the AMD Opteron™ 6100 Series processors to market allowed us to deliver an MCM design to market, which validated that technology. Having the SR5600 series chipsets, with more than a year under their belt, means that platform validation should be much easier for our partners. One of the biggest beneficiaries of a 32nm design is not necessarily a new technology added to the processor as much as it is the socket, chipset and platform work that happened ahead of the “Bulldozer” release.

    “How the cache subsystem looks like and how much L2 and L3 cache memory Bulldozer have?” - Marcin Szymanowicz


    As I stated in the first answer, we won’t give cache sizes, but I can talk about how the caches are laid out with respect to the module. The L1 cache is comprised of two components, an instruction cache and a data cache. The instruction cache is 64K and is shared between the 2 integer cores in the module. The data cache is 16K and there is one dedicated data cache for each core in the module. The L2 cache holds a mixture of both data and instructions and is shared by the two integer cores. If only one thread is active, it will have access to the entire L2 cache. The L3 cache is shared at the die level, so on the “Interlagos” processor you will have 2 separate L3 caches, one for each die. On the “Valencia” processor you will have one L3 cache because there is only one processor die.

    “Why don’t you for example publish the list of patents related to technologies implemented by Bulldozer, and the list of patents which appeared during the last years but are NOT implemented by Bulldozer? In addition, a simple list of non-patented technologies implemented by Bulldozer would be very helpful as well.” – Square Symbol


    If only it were that easy. AMD has hundreds of patents each year based on the research of our engineering teams. There are people who spend many hours combing through public records trying to piece together all of the details of what our architecture might or might not be. For competitive reasons, we aren’t going to publish such a list, before or even after a processor has been released. For companies like AMD that live in a highly technical world, many of these details help give us a competitive edge. To customers, it’s not usually the technology in the processor, but it’s those “3 P’s” that matter: What is the Price? What is the Performance? And what is the Power efficiency?

    “As far as power usage goes, from what I understand BD is supposed to be taking power management features to a level of granularity that hasn’t been seen yet with consumer/business grade CPUs. Will those new features be available to current MC users or will a platform upgrade be necessary?” – Jeremy Stewart


    ”Bulldozer’s” features that are designed to increase power savings reside in the processor and BIOS, not the platform. Many customers with existing AMD Opteron™ 6000 Series platforms should be able to upgrade to “Bulldozer”-based “Interlagos” processors when they are available. The reason that I say “many” and “should” (in addition to having lawyers review my blogs) is that an upgrade is not necessarily something that AMD can guarantee – your ability to upgrade will depend upon your individual system configuration, and that’s something we cannot control.
    “Interlagos” processors will be socket compatible and are designed to have the same power/thermals, so it should work with existing thermal solutions. However, we don’t control the system BIOS, nor the system support. It is best for you to check with your system or motherboard vendor to determine whether your system can be upgraded.
    The vast majority of servers are not upgraded, but the more important question is whether the platform changes between the current processors and the new ones. Having specified the AMD Opteron™ 6000 series platform to work with both processors, there should be no need for the platform to change for many systems, making it far easier for customers to manage multiple generations of processors side by side.
    http://blogs.amd.com/work/2010/10/04...stions-part-4/

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