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Thread: AMD's Carrizo APU Details Leaked - SoC for The Mainstream

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    Default AMD's Carrizo APU Details Leaked - SoC for The Mainstream

    Interesting article from Brightsideofnews. Post your thoughts on this.


    In January AMD launched the Kaveri APU, which is the first APU product with HSA support. While until today only two desktop SKUs have been launched, with more planned down the road as well as a full notebook lineup, AMD is already working hard on the next generation APU. The new chip's codename is Carrizo and I had the chance to look at a document aimed at developers "Preliminary BIOS and Kernel Developer’s Guide (BKDG) for AMD Family 15h Models 60h-6Fh Processors“, which documents some of the new features of this APU.

    The CPU cores will be upgraded from Steamroller to Excavator. Thanks to a patch AMD submitted to the GCC project last September, we know that Excavator will add support for AVX2, BMI2, MOVBE and RDRAND instruction set extensions. Except for the TSX extensions found on select models, this brings the core to feature parity with Haswell. Other than that not much is known about any enhancements Excavator will bring to the table. The document I have seen is vague and only mentions "IPC/Architectural changes" which alludes to the optimizations AMD has planned for Excavator back when the roadmap for the Bulldozer architecture was laid out. No further changes regarding cache sizes are mentioned.

    The GPU of Carrizo will stay largely the same as in Kaveri. The document mentions "Volcanic Island tiles", which technically Kaveri also has as it is architecturally on the same level as the Hawaii GPU. While I don't want to preclude that it contains architectural tweaks not mentioned in this document, for now no information on any such enhancements is known. It is not mentioned whether the number of CUs will change. Given we know that Carrizo will be manufactured at the 28nm node, albeit a different process than Kaveri, it is unlikely AMD adds more compute units to the GPU...............

    Finish reading the rest here Exclusive: AMD's Carrizo APU Details Leaked - SoC for The Mainstream - Bright Side Of News*
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    Default Re: AMD's Carrizo APU Details Leaked - SoC for The Mainstream

    Hmm sounds good. Nice updates like PCIe 3.0 and DDR4. I'm curious if in comparing to Haswell that means we'll see some single thread performance boosts but outside of that, most of the info does seem too early to tell.
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    Default Re: AMD's Carrizo APU Details Leaked - SoC for The Mainstream

    Quote Originally Posted by joshjaks View Post
    Hmm sounds good. Nice updates like PCIe 3.0 and DDR4. I'm curious if in comparing to Haswell that means we'll see some single thread performance boosts but outside of that, most of the info does seem too early to tell.

    All lanes moving over the PCI-e 3.0 is a nice upgrade and DDR4 is most def a big upgrade.

    Doubtful. Seems like that were making more of a comparison to instruction set extension support, not actually core performance. When these are set to be released, comparing it to what will be last gen for Intel doesnt bode well for the long term outlook of AMD. If you are constantly one to two gens behind you will not be around long enough to worry about playing catch up. So I am hoping for comparable performance to Intels next gen up to the I5 range. We know AMD has nothing for the i7 range.
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    Default Re: AMD's Carrizo APU Details Leaked - SoC for The Mainstream

    Quote Originally Posted by Cyberburnout View Post
    AVX2, BMI2, MOVBE and RDRAND instruction set extensions. Except for the TSX extensions found on select models
    What do the bolded items mean? i am intrigued, till i get to here and go side lined, not knowing what they mean

    I just got that 7850 last weekend, i either had a bad chip or board, but got beyond frustrated and returned them both, going to wait for the Guru to do the review on it, before i make the decision to get it again, or maybe just go about and due a rebuild with the FX line.

    I am guessing it will most likely still the same Chipset, as it is so new the A88?

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    Default Re: AMD's Carrizo APU Details Leaked - SoC for The Mainstream

    Quote Originally Posted by Carnyakam View Post
    What do the bolded items mean? i am intrigued, till i get to here and go side lined, not knowing what they mean

    I just got that 7850 last weekend, i either had a bad chip or board, but got beyond frustrated and returned them both, going to wait for the Guru to do the review on it, before i make the decision to get it again, or maybe just go about and due a rebuild with the FX line.

    I am guessing it will most likely still the same Chipset, as it is so new the A88?
    RdRand (also RDRAND; previously known as Bull Mountain[1]) is an instruction for returning random numbers from an Intel on-chip hardware random number generator.[2] RdRand is available in Ivy Bridge processors[note 1] and is part of the Intel 64 and IA-32 instruction set architectures. The random number generator is compliant with security and cryptographic standards such as NIST SP 800-90A,[4] FIPS 140-2, and ANSI X9.82.[2]

    Movbe was introduced for Intel’s Atom, and is quite useful for embedded applications that deal with storage and networking, since TCP/IP is big-endian.

    Bit Manipulation Instructions Sets (BMI sets) are extensions to the x86 instruction set architecture for microprocessors from Intel and AMD. The purpose of these instruction sets is to improve the speed of bit manipulation. All the instructions in these sets are non-SIMD and operate only on general-purpose registers.



    Advanced Vector Extensions (AVX) are extensions to the x86 instruction set architecture for microprocessors from Intel and AMD proposed by Intel in March 2008 and first supported by Intel with the Sandy Bridge processor shipping in Q1 2011 and later on by AMD with the Bulldozer processor shipping in Q3 2011. AVX provides new features, new instructions and a new coding scheme.
    AVX2 expands most integer commands to 256 bits and introduces FMA. AVX-512 expands AVX to 512-bit support utilizing a new EVEX prefix encoding proposed by Intel in July 2013 and first supported by Intel with the Knights Landing processor scheduled to ship in 2015.[1]


    The Guru to do a review on what again?






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  6. The following user thanks Cyberburnout For this above post:

    Carnyakam (22-03-2014)

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    Default Re: AMD's Carrizo APU Details Leaked - SoC for The Mainstream

    Kenny to do the Review on the 7850, and TY for the explination.

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    Default Re: AMD's Carrizo APU Details Leaked - SoC for The Mainstream

    Quote Originally Posted by Carnyakam View Post
    Kenny to do the Review on the 7850, and TY for the explination.
    Gotcha!! Dont know if we are going to do the review on the 7850. There was some issues with samples going out to a lot of sites. It is getting to the point of not being worth covering because it has been out for so long. We will be covering boards in reviews. That is because we purchased our own 7850s for board testing. We technically could do a review on the APU but we are not in the habit of giving free coverage for products when a sample was not provided. AMD didnt do anything wrong and we are on great terms with them. There has just been a lot of interest in Kaveria and they are selling at a rapid pace. If I was them I wouldn't provide many samples either. Its already a very hot item. If they do end up providing a sample we will be more then happy to cover it.
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    Default Re: AMD's Carrizo APU Details Leaked - SoC for The Mainstream

    yeah the prices have been going up at a rapid rate, i am intrested in seeing what this new one will offer!

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